Skip to content

iCE40 Floorplan Viewer

An interactive browser-based visualization tool for iCE40 FPGA floorplans. It renders the physical layout of logic cells, I/O blocks, and routing resources, making it possible to visually inspect how designs are placed and routed on the chip.

Open iCE40 Viewer

Key Features

  • Interactive floorplan — zoom, pan, and click on individual tiles and cells
  • Browser-based — no installation required, runs entirely in the browser
  • iCE40 family support — visualize HX1K, UP5K, and other iCE40 device layouts
  • Bitstream inspection — load .asc files to see how a design maps onto the physical chip

Role in Evolvable Hardware

The iCE40 Viewer is particularly useful for evolvable hardware research because it allows researchers to visually inspect evolved bitstreams. After an evolutionary run produces a circuit, the viewer can show exactly which logic cells and routing paths the evolution utilized — including unconventional connections that exploit analog physical properties of the FPGA.

Project Use